Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others.
As memory density has increased, intermittent failure has appeared in some devices, such as DRAM memories, which may experience failures due to repeated access to a particular row of memory cells (e.g., cells coupled to an access line) within a refresh window associated with the cells. For example, rows physically adjacent to a row being frequently accessed within the refresh window have an increased probability of experiencing data corruption. The repeated access of a particular row can be referred to as a “hammering” event, and the hammering of a row can cause issues such as migration across a passgate, for example. Leakage and parasitic currents caused by the hammering of a row can cause data corruption in a non-accessed physically adjacent row, which may be referred to as a neighbor row or victim row. The resulting corruption issue may be referred to as hammer disturb and/or row hammer disturb, for instance.
Some previous approaches to reducing the adverse effects of row hammering on adjacent rows include refreshing adjacent rows responsive to a determination that a hammering event has occurred. For example, responsive to determining that a particular row has been the target of repeated accesses (e.g., the row has undergone more than a threshold number of accesses within a refresh period), its physically adjacent neighbor rows can be selected for a targeted refresh operation, which may be referred to as a row hammer refresh operation.
The row hammer effect is due to the nature of a memory cell, which can include one transistor and one capacitor. The charge state of a capacitor is what determines whether a DRAM cell stores a “1” or “0” as a binary value. In addition, a large number of DRAM cells are packed tightly together. The closely packed cells can cause an activated capacitor to have an effect on a charge of an adjacent capacitor, especially when one of the cells is rapidly activated (e.g., a row hammer effect). In addition, the capacitors can have a natural discharge rate and may be rewritten in order to compensate for this discharge, referred to as “refreshing.”